Chiplet Interconnect Patent Damages: How Courts Apportion Royalties in Multi-Die AI Chips

1. The Shift from Monolithic to Multi-Chiplet Architectures

For decades, semiconductor scaling followed a simple playbook: shrink transistors, grow die area, ship a single monolithic chip. But Moore’s Law has hit a physical wall. The reticle limit of photolithographic equipment constrains monolithic dies to approximately 800 mm², and yield rates plummet as die area approaches that ceiling. The industry’s answer is heterogeneous integration—splitting a single logical processor into multiple smaller chiplets connected by high-bandwidth interconnects.

Two architectures dominate the AI accelerator market, and their design philosophies carry profound implications for patent damages apportionment.

NVIDIA Blackwell (B200) uses a dual-die design connected via NVLink-C2C at 10 TB/s of bidirectional bandwidth. With 208 billion transistors split across two dies, the B200 presents itself to software as a single unified GPU—applications see one device, one memory space, one logical entity. The interconnect is invisible to the programmer, and NVIDIA has engineered it to be invisible to the operating system as well.

AMD Instinct (MI300X) takes a fundamentally different approach. It combines 8 XCD (Accelerator Complex Dies) and 4 IOD (I/O Dies) via Infinity Fabric, using 3D stacking to pack approximately 153 billion transistors into a single package. Unlike Blackwell, the MI300X exposes its topology: software must be NUMA-aware, and the discrete XCD/IOD cluster architecture is visible to the system scheduler.

This distinction—NVIDIA’s “logical unity” versus AMD’s “modular heterogeneity”—is not merely a design preference. It directly affects how courts evaluate the interconnect’s contribution to the overall product. When the interconnect is seamless and invisible, plaintiffs argue it is inseparable from the whole. When it is modular and exposed, defendants argue it is a commodity component.

2. The Onesta IP v. NVIDIA Case: U.S. Patent No. 11,841,803

The collision between chiplet architecture and patent law is playing out in real time at the U.S. International Trade Commission. ITC Investigation 337-TA-1450 was filed by Onesta IP, a non-practicing entity that acquired U.S. Patent No. 11,841,803 from AMD. The irony is not lost on the industry: a patent originally developed by one chiplet pioneer is now being asserted against another.

The ’803 patentcovers “GPU chiplets with high-bandwidth crosslinks”—specifically, passive crosslinks such as silicon bridges or interposers that are dedicated to inter-chiplet communication. The claimed invention focuses on the physical interconnect layer, not the compute dies themselves.

NVIDIA’s defense, filed under IPR2026-00011 at the Patent Trial and Appeal Board, makes two principal arguments. First, NVIDIA contends that NVLink-C2C is not a passive crosslink—it contains active PHY (physical layer) circuitry and controller logic, placing it outside the patent’s claims. Second, NVIDIA cites the Collins patent, an Intel Embedded Multi-Die Interconnect Bridge (EMIB) predecessor, as invalidating prior art.

Onesta IP’s response relies on reverse-engineering analysis that claims Blackwell’s trace routing implements the claimed cache coherency and unified logical view described in the ’803 patent. Onesta argues that regardless of whether the C2C link contains active elements, it functionally performs the same role—creating a unified memory space across physically separate dies—and therefore falls within the patent’s scope.

The ITC’s final determination is scheduled for November 30, 2026. The outcome will set a significant precedent for how interconnect patents are construed across the chiplet ecosystem.

The apportionment tension is stark: if infringement is limited to the C2C interconnect layer, the royalty base should arguably be the silicon bridge component—worth approximately $100—not the entire $40,000 B200 module. The difference between those two baselines represents orders of magnitude in potential damages.

3. Damages Apportionment Law: SSPPU to EcoFactor (2025)

The statutory basis for all patent damages is 35 U.S.C. § 284, which requires damages “adequate to compensate for the infringement, but in no event less than a reasonable royalty.” In multi-component products like chiplet-based GPUs, the critical question is which component serves as the royalty base.

The damages formula is deceptively simple: D = B × R × V—where D is total damages, B is the royalty base, R is the royalty rate, and V is the volume of infringing units sold. Each variable, however, is intensely contested.

4. Performance Attribution: Solving the “1-of-10” Problem

When the physical die area of a component does not reflect its functional value, courts face what practitioners call the “1-of-10” problem: the interconnect occupies a tiny fraction of the package’s silicon area but contributes an outsized share of the system’s throughput. A purely area-based apportionment would drastically undervalue the interconnect; a revenue-based approach would overvalue it. Courts have increasingly turned to performance-based attribution methods.

The precedent is WARF v. Apple, where the court accepted a regression analysis to calculate the processor speed premium attributable to the patented technology. By isolating the performance delta with and without the invention, the expert could assign a percentage contribution that mapped directly to a royalty rate.

In 2026, two analytical methods are emerging as the standard for chiplet apportionment:

• Digital twin simulation: Using EDA platforms from Synopsys or Cadence, experts can build a digital twin of the accused chip and simulate its performance with and without the infringing interconnect. This provides quantifiable, repeatable evidence of the interconnect’s contribution—exactly the kind of rigorous methodology that EcoFactor now demands.
• LLM inference throughput analysis: For AI accelerators, the performance impact of removing a passive crosslink is dramatic and measurable. Without the C2C interconnect, the B200’s inter-die bandwidth would drop from 10 TB/s to PCIe 5.0 speeds (~128 GB/s)—a roughly 78x reduction. The resulting impact on trillion-parameter model inference latency is directly quantifiable through benchmark suites.

The 2024 Federal Circuit decision in Brumfield v. IBG further expanded the analytical toolkit by establishing that foreign economic activity can factor into a reasonable royalty calculation when domestic infringement generates overseas value. For NVIDIA, whose Blackwell GPUs power data centers worldwide, this means the damages base could extend beyond U.S. sales.

The causal logic is straightforward: if the infringing interconnect contributes a measurable 30% performance gain, that 30% becomes the apportionment ceiling—the maximum share of product value attributable to the patented technology. Whether the actual royalty rate approaches that ceiling depends on the remaining Georgia-Pacific factors.

5. UCIe 2.0 and Multi-Vendor IP Liability

The Universal Chiplet Interconnect Express (UCIe) consortium— whose members include Intel, AMD, NVIDIA, TSMC, and Samsung—aims to create a USB-like plug-and-play ecosystem for chiplets. The vision is compelling: standardized interfaces that allow any vendor’s compute chiplet to connect with any vendor’s I/O die. But standardization creates new patent liability vectors.

The UCIe IP policy provides cross-licensing for “necessary claims” only—patents that are essential to implementing the base UCIe specification. Proprietary optimizations layered on top, such as NVIDIA’s NVLink protocol enhancements or AMD’s Infinity Fabric coherency extensions, are not coveredby the consortium’s cross-license. This gap leaves significant IP exposure for any company that implements more than the bare standard.

The supply chain liability question is particularly acute. If an I/O chiplet sourced from a third-party IP vendor like Alphawave or Synopsys is found to infringe a patent, NVIDIA as the system integrator bears primary liabilityto the patent holder. NVIDIA can then seek indemnification from the supplier—but indemnification clauses are typically capped at the contract value, which is wholly insufficient to cover verdicts that could exceed $100 million.

6. ITC Investigation Strategy and Settlement Economics

ITC Investigation 337-TA-1450 exemplifies the classic NPE dual-track strategy: file simultaneously at the ITC and in federal district court. The ITC track provides speed and leverage; the district court track provides monetary damages. The combination creates a powerful settlement dynamic.

The ITC’s unique power lies in its ability to issue exclusion ordersthat block all infringing imports from entering the United States—not merely monetary compensation, but a physical bar on the product. For AI accelerators, the implications are staggering. Banning Blackwell B200 modules from the U.S. market would disrupt every major cloud provider’s AI infrastructure buildout and raise serious questions about national AI competitiveness.

NVIDIA’s defensive strategy centers on inter partes review (IPR) at the PTABunder docket IPR2026-00011, seeking to invalidate the ’803 patent entirely. If the PTAB institutes review and finds the claims unpatentable, the ITC investigation becomes moot. This is a well-worn playbook: between 2012 and 2025, IPR petitions were filed in conjunction with approximately 70% of ITC investigations involving semiconductor patents.

The settlement dynamics in chiplet interconnect cases are driven by an asymmetry of risk. For the plaintiff, a granular apportionmentanalysis could shrink damages to a fraction of the module price—the $100 silicon bridge rather than the $40,000 module. For the defendant, an exclusion order represents potential market losses worth billions. Most ITC investigations settle after the Administrative Law Judge issues an Initial Determination, when both sides have maximum clarity on the likely outcome.

The settlement calculus is ultimately straightforward: for NVIDIA, the option value of keeping the B200 in the U.S. marketfar exceeds any SSPPU-based reasonable royalty. A rational settlement would fall somewhere between the granular apportionment floor and the cost of market exclusion—a range that, in this case, likely spans from tens of millions to low hundreds of millions of dollars.

7. Toward a Fair Apportionment Framework for Heterogeneous Integration

Neither the traditional entire market value approach nor a simplistic area-based apportionmentproduces fair results in the chiplet era. The former inflates damages by tying them to a product whose value derives from dozens of technologies; the latter deflates them by ignoring the interconnect’s critical role in enabling system-level performance.

What the industry needs is a framework that distinguishes between “commodity interconnect”—basic I/O that any standard protocol could provide—and “value-adding features”such as proprietary coherency protocols, bandwidth optimizations, and unified memory addressing that differentiate one chiplet architecture from another. The patented feature’s contribution should be measured against this spectrum, not against the full module price.

EcoFactor v. Google has raised the evidence quality bar for all future chiplet damages cases. Expert reports that rely on textual claim-chart analysis alone will face exclusion under tightened Rule 702 scrutiny. The 2026 standard increasingly requires experts to integrate EDA simulation data—digital twin models, bandwidth regression analyses, and quantified performance deltas—into their damages testimony. Legal analysis without engineering evidence is no longer sufficient.

Looking ahead, the industry may need a standard-essential patent (SEP)-like royalty pool mechanismfor UCIe and chiplet-related patents. Without coordinated licensing, royalty stacking across the compute die, I/O die, interposer, and interconnect layers could erode margins to the point where heterogeneous integration becomes economically nonviable. The parallels to the wireless industry’s FRAND licensing framework are instructive, though the chiplet ecosystem’s greater architectural diversity makes direct transplantation challenging.

The legal and technical co-evolution of chiplet apportionment doctrine is just beginning. As the ITC rules on 337-TA-1450, as the PTAB decides IPR2026-00011, and as UCIe 2.0 drives broader adoption of multi-vendor chiplet architectures, the precedents set in 2026 will define how semiconductor patent damages are calculated for the next decade.

Sources

Selected primary or official reference materials used for this guide.

• 35 U.S.C. § 284 — Damages
• NVIDIA Blackwell Architecture
• AMD CDNA 3 Architecture White Paper
• ITC Investigation 337-TA-1450
• UCIe Consortium — Specification
• EcoFactor v. Google — Federal Circuit (en banc, 2025)